- OPTIMIZED SIGNED MULTIPLIER FOR FPGA HARDWARE ACCELERATORS: ENERGY EFFICIENCY AND LOW LATENCY
N. Lakshmi Durga1, K.Teja Sri2, CH.Abhinaya3, K.Geethika4, K.Ramya Sravanthi5, G.Suchithra6; ELURU COLLEGE OF ENGINEERING AND TECHNOLOGY, ELURU
Page No: 01-05
DOI:16.10089.IJR.2025.V14I04.285311.141178
- OPTIMIZED WALLACE TREE MULTIPLIER WITH PARALLEL PREFIX ADDER FOR HIGH-PERFORMANCE VLSI CIRCUITS
S. Rama Tulasi1, K.Gnana Prabha Sri2, G.Prasanna3, B.Ankitha4, CH.Devi Sri5; ELURU COLLEGE OF ENGINEERING AND TECHNOLOGY, ELURU
Page No: 06-10
DOI:16.10089.IJR.2025.V14I04.285311.141180
- LOW-POWER, HIGH-SPEED APPROXIMATE MULTIPLIER FOR ENERGYEFFICIENT COMPUTING
B. Durga Rao1, A.Venkata Narayana2, A.Uma Mahesh3, G.Rajesh4, B.Srinivasulu5; ELURU COLLEGE OF ENGINEERING AND TECHNOLOGY, ELURU
Page No: 11-16
DOI:16.10089.IJR.2025.V14I04.285311.141181
- EFFICIENT VLSI IMPLEMENTATION OF A HIGH-SPEED THREE-OPERAND BINARY ADDER
N. Lakshmi Durga1, V.Swapna2, S.Meena Sri3, S.Lakshmi Lalini4, K.M.D.Mounika; ELURU COLLEGE OF ENGINEERING AND TECHNOLOGY, ELURU
Page No: 17-21
DOI:16.10089.IJR.2025.V14I04.285311.141182
- OPTIMIZED MULTI-ACCUMULATE (MAC) UNIT FOR HIGHPERFORMANCE COMPUTING
B. Durga Rao1, K.Mohan2, M.Satyanandham3, M.Nagasai Kiran4, Y.Durga Prasanth; ELURU COLLEGE OF ENGINEERING AND TECHNOLOGY, ELURU
Page No: 22-26
DOI:16.10089.IJR.2025.V14I04.285311.141183
- HIGH-PERFORMANCE VIRTEX-7 FPGA IMPLEMENTATION OF 256-BIT AES WITH KEY SCHEDULE AND SUBBYTES OPTIMIZATION
R. Bindu Pavani1, D.Victor Babu2, G.Mahesh3, K.Akhil Kumar4, K.Harsha Vardhan5; ELURU COLLEGE OF ENGINEERING AND TECHNOLOGY, ELURU
Page No: 27-31
DOI:16.10089.IJR.2025.V14I04.285311.141184
- SIGNATURE VERIFICATION USING DEEP LEARNING
1 Dr. D HEMA, Ph.D., P. GOPI CHAND 2, P. LAKSHMI PAVANI 3, M. SRINIVAS 4, S. PURNA DURGA PRASANTH 5.; AMRITA SAI INSTITUTE OF SCIENCE AND TECHNOLOGY, PARITALA, VIJAYAWADA, ANDHRA PRADESH 521180.
Page No: 32-36
DOI:16.10089.IJR.2025.V14I04.285311.141185